1. Field
The subject technology relates generally to electronic devices and clock generation or utilization, and more specifically to methods and apparatus for generating or utilizing one or more cycle-swallowed clock signals.
2. Background
One approach to generate all of the clock signals needed in modern electronic devices is to employ different phase-locked loops (PLLs) for different clocks, or one PLL for the least-common multiple of the desired clock frequencies as a reference so that one can obtain each of the desired clock signals using frequency dividers. This is impractical from the area/power standpoint. Furthermore, reference frequencies may drift as a result of a frequency drift of a crystal oscillator, temperature variations, and/or supply voltage variations, leading to non-integer division ratios, which are difficult to implement.